The most significant use of electronic memory chips, and in particular dynamic random access memory (DRAM) chips, is in the construction personal computers. In such applications, each memory device is expected to be fully functional; even only partially defective memory chips are normally not used. Thus, various techniques have been developed to increase memory chip manufacturing yields, especially in state of the art chips which have not reached "yield maturity" (yield maturity is normally achieved only as the manufacturing process is refined over time).
One technique for improving yield is replacement of defective cells identified during wafer testing with "spare" or "redundant" cells included in each memory cell array. In particular, the use of on-chip redundant rows and columns of cells for replacing defective rows and columns in a dynamic random access memory (DRAM) cell array is well established in the art. The basics of defective cell replacement are set forth, for example, in Fitzgerald and Thomas, Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement, IBM Journal of Research and Development, Vol. 24, No. 3, May 1980.
Generally, in currently available DRAMs, the wordlines of the primary rows and the input/output devices of the sense amplifiers of the primary columns of each array or bank are connected to the corresponding row and column address decoders by programmable links, typically laser programmable fuses or electrically-programmable read-only memory (EPROM) cells. During probe testing, defective rows and/or columns are identified and then functionally removed from the remainder of the array by programming the appropriate links as required to disconnect each defective row or column from the associated address decoder.
In a typical DRAM, the array(s) of each chip is fabricated with a given number of spare rows and spare columns (along with corresponding spare sense amplifiers). Typically, 5% of the rows and columns for a given array are redundant cells, at the most. Each spare row and column is associated with a programable address decoder/driver. When a defective row or column is functionally removed from the array, the address decoder circuitry for a selected spare row/column in the array is programmed (again using programmable links) to respond to the same address to which the address decoder circuitry of the defective row/column was to respond. As a result, addresses to the defective row/column are redirected (steered) to a good redundant row/column and accesses made without error.
Current repair techniques however do not allow for the replacement of a defective row or column in one array or device with a good redundant column of another array or device without the payment of significant cost and performance penalties. Typically, the cells of each DRAM device are addressable by a fixed set of row/column address bits. In a multiple device memory bank, the row/column address set (space) is typically the same for all devices within each bank to minimize circuitry overhead. For example, assume that a bank of four 256k.times.16 DRAMs is supporting a 64-bit data bus. Then to access a 64-bit word, each device receives the same eight address bits A0-A7 simultaneously. Thus, for example, if Row 0 at Address 0 in Device A is defective and Row 0 at Address 0 in Bank B is operational, then Row 0 of Device A cannot simply be replaced by disconnecting it from the associated row decoder and programing a redundant row in Bank B to respond to Address 0, since Address 0 already maps to an operational row in Device B.
The inability to efficiently perform device to device replacements of defective rows and columns results in the inability to optimize device yields and thus eventually reduce system cost. For instance, after wafer testing, one device may have more defective rows (or columns) than redundant rows (or columns) available for repair while another device on the same bank may have an excess of redundant rows (or columns). Currently, the device with excess defective cells must be discarded since there is no available known technique for matching it with the device with excess redundant cells and performing inter-device cell replacement, at reasonable cost (of course, one can have redundant devices).
Thus, the need has arisen for memory devices and associated system architectures which allow for replacement of a defective row or column of a given memory device with an operational row or column of another memory device. This feature would allow for memory devices which normally would be discarded to be salvaged with the aid of a similar device having an excess of operational spare cells. Such a scheme will reduce system costs, with very little performance penalty (memory latency, power dissipation, minimal system overhead, etc.)